As electronic devices become lighter, thinner, shorter, and smaller, an important factor in achieving such reductions is high density mounting of semiconductor packages, as key components of such electronic devices.
In a computer or other electronic device, sizes of semiconductor devices, such as a random access memory (RAM) and a flash memory, increase to achieve an increase in memory capacity, while packages are miniaturized. Approaches for reducing package size have been developed. For example, according to one approach, a stack-type semiconductor package is configured to include a plurality of stacked semiconductor chips or semiconductor device packages. According to another approach, a semiconductor module having a plurality of semiconductor chips, a plurality of semiconductor device packages, and/or stack-type semiconductor packages are mounted on at least one surface of a printed circuit board (PCB).
Such packages may be classified into a semiconductor chip stack-type package, which is identical to a multi-chip package (MCP) including a plurality of semiconductor chips having different functions. The semiconductor chip stack-type package includes a plurality of stacked semiconductor chips to realize a high capacity.
The semiconductor chip stack-type package may be a product or application of a three-dimensional (3D) arrangement technique. With the 3D arrangement technique, a plurality of memory chips is stacked to improve the integrity of a semiconductor memory. As a semiconductor chip stack-type package, a multi-channel DRAM device is developed to satisfy a need for high-density and high-capacity memories and to improve system performance.
Since a multi-channel semiconductor memory device has a structure wherein a plurality of semiconductor chips (or channel memories) is stacked, through-silicon vias (TSVs) may be applied to the multi-channel semiconductor memory device. A through-silicon via may be used as conductive lines between a plurality of memories. The through-silicon via may function as a signal transfer line for transferring a command signal or an address signal applied from a memory controller or a line for transferring data.
In such channel memories, a plurality of vias is formed at semiconductor chips to penetrate a die vertically.
In a conventional multi-channel DRAM device, since a command signal and an address signal are applied to each memory device independently, each channel coupled with each memory necessitates dedicated command and address transfer lines. Accordingly, a die area occupied by through-silicon vias is relatively large. For example, if a command/address line number per channel is 23 and a channel number is 16, one die may require 368 through-silicon vias.
An increase in the number of through-silicon vias causes an increase in chip die size. As a result, a yield of a multi-channel semiconductor memory device is lowered and cost is increased.